1. Field of the Invention
The present invention relates to an adaptive equalizer correcting a filter coefficient (tap coefficient) for an input signal so as to minimize the error between an output signal and a reference signal. Particularly, the present invention relates to an adaptive equalizer that can reduce the delay time of a critical path, and a method of designing that adaptive equalizer.
2. Description of the Background Art
In the field of cable television service (CATV) and the like, the usage of digital communication that employs digital signals impervious to noise instead of analog signals is now practically in progress as a high speed data communication system replacing the conventional analog communication. The presence of multiple delay waves arising from multipath propagation caused by wave reflection at the end of a non-terminated cable has been ascertained in the digital cable television service. The presence of such multiple delay waves causes multiple wave fading due to the interference between the main wave and the delay waves. When the amplitude of a delay wave approximates to that of the main wave, frequency selective fading occurs in which a particular frequency component is attenuated significantly, to result in generation of waveform distortion. This waveform distortion may induces code error by inter-symbol interference. It is necessary to prevent generation of frequency selective fading caused by such multiple delay waves in high speed digital transmission.
An adaptive equalizer that adaptively removes inter-symbol interference arising from multipath propagation has been studied as one technique to solve this frequency selective fading. In digital communication, data referred to as xe2x80x9csymbolxe2x80x9d is transmitted at every predetermined period referred to as xe2x80x9csymbol cyclexe2x80x9d. In an ideal transmission path free from multipath propagation, one symbol will not affect another symbol transmitted at another symbol cycle. However, when multiple delay waves are generated by multipath propagation, a plurality of symbols will arrive at the reception side in the same symbol cycle by the delay waves. More specifically, inter-symbol interference occurs to disable proper reception and reproduction of transmitted signals.
The above-described problem of frequency selective fading occurs, not only in wire communication utilizing a cable, but also in wireless transmission paths utilizing microwaves.
The LMS (Least Mean Square Error Algorithm) architecture is often employed for the adaptive equalizer used in digital communication. The basic structure of this LMS architecture includes an FIR (Finite Impulse Response) filter.
FIG. 11 shows the basic structure of a conventional adaptive equalizer. This adaptive equalizer includes a filter processing unit 1 applying a filtering process on an input signal x(n), an error detection circuit 2 obtaining an error between an output signal y(n) of filter processing unit 1 and a reference signal d(n), and a coefficient update circuit 3 correcting tap coefficients (filter coefficients) h0xcx9chNxe2x88x921 of filter processing unit 1 according to an output signal e(n) of error detection circuit 2.
Filter processing unit 1 is formed of a direct type discrete filter. A discrete input signal x(n) extracted from the response characteristics at the time region is filtered according to tap coefficients h0xcx9chNxe2x88x921, to produce a discrete output signal y(n). Reference signal d(n) is output from an identification circuit (or determination circuit) that estimates a final output signal (code) from output signal y(n) of filter processing unit 1.
Discrete filter 1 includes delay elements SR0xcx9cSRNxe2x88x921 connected in series and each formed of a shift register delaying input signal x(n) by one clock cycle period, multipliers M0xcx9cMNxe2x88x921 multiplying the output signals of delay elements SR0xcx9cSRNxe2x88x921 by corresponding tap coefficients h0xcx9chNxe2x88x921, and adders A1xcx9cANxe2x88x921 provided corresponding to multipliers M1xcx9cMNxe2x88x921, respectively, for adding the output signals of preceding adders with the output signals of corresponding multipliers to transmit the addition result to succeeding adders. Output signal y(n) is generated from the last stage adder ANxe2x88x921. Here, the output nodes of delay elements SR0xcx9cSRNxe2x88x921 are generally referred to as xe2x80x9ctapsxe2x80x9d. Therefore, direct filter 1 is an N-tap filter. As to xe2x80x9cZxe2x88x921xe2x80x9d of delay elements SR0xcx9cSRNxe2x88x921, the exponent indicates the amount of delay.
Error detection circuit 2 is generally formed by an adder. Output signal y(n) is subtracted from reference signal d(n). That difference value is output as the error caused by frequency selective fading.
Coefficient update circuit 3 includes a multiplier Me multiplying error signal e(n) by step size xcexc, and tap coefficient update stages provided corresponding to tap coefficients h0xcx9chNxe2x88x921, respectively. The tap coefficient update stages have the same structure, and each include a delay element CSR (CSR0xcx9cCSRNxe2x88x921) formed of a shift register that delays the signal from the preceding stage by one clock cycle, a multiplier CM (CM0xcx9cCMNxe2x88x921) multiplying an output signal xcexcxc2x7e(n) of multiplier Me by the output signal of a corresponding delay element, an adder CA (CA0xcx9cCANxe2x88x921) receiving the output signal of multiplier CM, and a delay element CSF (CSF0xcx9cCSFNxe2x88x921) formed of a shift register that delays the output signal of adder CA by one clock cycle. The output signal of delay element CSF is applied to adder CA. Adder CA adds the output signal of a corresponding multiplier CM with the output signal of a corresponding delay element CSF to provide the addition result to delay element CSF again.
Step size xcexc indicates the step size of a discrete value of discrete input signal x(n) to normalize the error signal by multiplier Me. This step size is generally a multiple of 2. Multiplier Me is formed of a bit shift circuit that shifts error signal e(n) towards the higher bit in order to multiply error signal e(n) by step size xcexc represented by 2 raised to the power. The operation of the adaptive equalizer shown in FIG. 11 will be described now.
Each of delay elements SR0xcx9cSRNxe2x88x921, CSF0xcx9cCSFNxe2x88x921, and CSR0xcx9cCSRNxe2x88x921 carries out a shift operation according to a clock signal not shown to implement delay of one clock cycle. Output signal y(n) of filter processing unit 1 is related to input signal x(n) by the following equation.
y(n)=xcexa3hkxc2x7x(nxe2x88x92k)
The summation is taken from 0 to Nxe2x88x921 for k. Error signal e(n) is represented by the difference between reference signal d(n) and output signal y(n). Therefore, the following equation is obtained.   "AutoLeftMatch"                                          e            ⁡                          (              n              )                                =                                    d              ⁡                              (                n                )                                      -                          y              ⁡                              (                n                )                                                                                  =                                    d              ⁡                              (                n                )                                      -                          ∑                              h                ⁢                                  xe2x80x83                                ⁢                                  k                  ·                                      x                    ⁡                                          (                                              n                        -                        k                                            )                                                                                                                                        =                                    d              ⁡                              (                n                )                                      -                                                            h                  T                                ⁡                                  (                  n                  )                                            ·                              X                ⁡                                  (                  n                  )                                                                        
where hT(n)=[h0(n), h1(n), . . . , hnxe2x88x921(n)],
XT=[x(n), x (nxe2x88x921), . . . , x (nxe2x88x92N+1)], and
T represents transposition.
The tap coefficient of the next cycle is related to the tap coefficient of the current cycle by the following equation.
h(n+1)=h(n)+xcexcxc2x7e(n)xc2x7X(n)
One tap coefficient hk is corrected according to the following equation.
hk(n+1)=hk(n)+xcexcxc2x7e(n)xc2x7x(nxe2x88x92k)
In the above equation, the output signals of shift registers (delay element) SR0 and CSR0 of the first input stage shown in FIG. 11 are set as x(n).
By correcting filter coefficients h0xcx9chNxe2x88x921 according to error signal e(n), the error component included in output signal y(n) may be removed to provide a more ideal output signal y(n).
In the adaptive equalizer shown in FIG. 11, the direct filter of filter processing unit 1 is formed of an FIR filter (non-recursive filter). Delay elements SR0xcx9cSRNxe2x88x921 each are a shift register transferring a signal according to a clock signal not shown. It is necessary to generate an output signal y(n) and also a tap coefficient for the next cycle within one cycle period of this clock signal. When the tap length of filter processing unit 1 is N, the critical path includes two multipliers M0 and CM0, N adders A1xcx9cANxe2x88x921, error detection circuit 2, and adder CA0 as shown by the solid line in FIG. 11. Here, multiplier Me carries out the operation of xcexcxc2x7e(n) by the bit shift operation, and has the delay ignored. Therefore, the delay in this critical path includes the delay of 2 multiplications +(N+2) additions.
Therefore, the critical path of the adaptive equalizer according to the LMS architecture depends on tap length N of filter processing unit 1, and becomes longer for the LMS architecture of a higher order. It is therefore difficult to improve the throughput, and there is a problem that it is difficult to carry out high speed processing such as image data transmission.
An object of the present invention is to provide an adaptive equalizer that can have the critical path shortened without increasing the hardware amount.
Another object of the present invention is to provide an adaptive equalizer having a critical path independent of the tap length.
In the adaptive equalizer of the present invention, the LMS architecture formed of a direct FIR filter is converted into an LMS architecture formed of a transposition FIR filter employing the look ahead conversion using the input signal preceding by L cycles and the retiming process of equivalent replacement of the signal delay.
According to a first aspect of the present invention, an adaptive equalizer includes a filter processing unit having a plurality of cascaded processing stages provided corresponding to taps. Each processing stage includes a multiplier to multiply an input signal by a corresponding tap coefficient, a delay stage delaying the output signal of a preceding processing stage, and an adder adding the output signal of the delay stage with the output signal of the multiplier to provide the addition result to the next stage. The first processing stage includes a multiplier multiplying the input signal by a corresponding tap coefficient for application to the next processing stage.
The adaptive equalizer of the first aspect includes a tap coefficient set circuit for setting a tap coefficient according to the error between the output signal of the filter processing stage and a reference signal. The tap coefficient set circuit includes a coefficient correction stage provided corresponding to each tap coefficient. Each coefficient correction has the same structure, and has the transfer function represented by the product of the an all zero filter transfer function and an all pole filter transfer function.
According to a second aspect of the present invention, an adaptive equalizer includes a filter processing unit having a plurality of processing stages connected in series in the forward and backward paths. Each processing stage includes a multiplier multiplying an applied signal by a corresponding tap coefficient, and an adder adding the output signal of the multiplier with the signal applied from the succeeding processing stage to transmit the addition result to the preceding stage. In the forward and backward paths of the processing stages, a delay stage that delays an applied signal by one cycle is interposed alternately.
The adaptive equalizer of the second aspect further includes a tap coefficient set circuit for setting a tap coefficient according to the error between the output signal of the filter processing stage and a reference signal. The tap coefficient set circuit includes coefficient correction stages having the same structure and provided corresponding to respective tap coefficients. Each coefficient correction has the transfer function given by the product of an all zero filter transfer function and an all pole filter transfer function.
According to a third aspect of the present invention, a method of designing an adaptive equalizer includes the steps of arranging a filter processing stage and a tap coefficient set circuit according to the LMS architecture using a direct filter structure, carrying out look ahead conversion for relating a tap coefficient preceding by L cycles with the tap coefficient of the next cycle to rearrange the filter processing stage and the tap coefficient set circuit, carrying out a retiming process for timing reorganization while maintaining the time relationship of signals to reorganize arrangement of the delay elements for realizing a transposition filter, and modifying the filter coefficient set stage to a filter stage having the transfer function of (1xe2x88x92Zxe2x88x92Lxe2x88x921)/(1xe2x88x92Zxe2x88x921) through equivalent conversion.
By carrying out equivalent conversion using look ahead conversion and retiming to modify the direct FIR filter according to the LMS architecture into a transposition FIR filter, a delay element operating in response to a clock signal can be interposed in the critical path. The critical path can be shortened without increasing the number of functional units. An adaptive equalizer operating at high speed can be realized.